ITA | ENG
B024258 - COMPUTER ARCHITECTURES
Main information
Teaching Language
Course Content
Suggested readings
Learning Objectives
Prerequisites
Teaching Methods
Further information
Type of Assessment
Course program
Academic Year 2016-17
Course year
Second year - First Semester
Belonging Department
Information Engineering (DINFO)
Modulo di sola Frequenza of
Scientific Area
ING-INF/05 - INFORMATION PROCESSING SYSTEMS
Credits
6
Teaching Hours
54
Teaching Term
19/09/2016 ⇒ 23/12/2016
Attendance required
No
Type of Evaluation
Giudizio Finale
Course Content
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Course program
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Lectureship
Teaching Language
Italian.
Course Content
Contenuti (Dipl.Sup.) CONTENUTI 500 Sì Fondamenti teorici e realizzazioni pratiche delle Reti Logiche e dei Microprocessori. Progetto di macchine sequenziali dedicate. Scrittura di semplici programmi in linguaggio assemblativo. Theoretical foundations and practical implementations of Logic Circuits and Microprocessors. Design of dedicated sequential machines. Writing of simple programs in assembly language.
Suggested readings (Search our library's catalogue)
BUCCI, Calcolatori elettronici - Architettura e organizzazione, McGraw-Hill Italia, 2009.
Learning Objectives
To know how to specify and implement simple synchronous, dedicated sequential machines, using the operating unit/control unit design paradism. To learn the basic architectural principles behind modern microprocessors and their hardware/software components.
Prerequisites
None. However, it is suggested to have attended the 1st year's course on Foundations of Computer Science and Programming.
Teaching Methods
Teaching: mainly at the blackboard, sometimes with PC+videoprojector. Additional material is suggested for home study. Further discussions and clarifications at student tutoring hours.
Further information
None.
Type of Assessment
The examination includes a written test and an oral test, the latter typically one week later than the other. The written test is usually subdivided into two parts. The first concerns the design of a dedicated sequential machine. In the second part, the student is requested to implement (machine code, operating unit, control unit) a single machine instruction on a CISC-like microprocessor. Alternative exercises focus on the measure/comparison of microprocessor performances, or on writing simple programs in assembly language. The oral test includes theoretical subjects and simple exercises.
Course program
1st PART – Logic Circuits:
Representation of signed/unsigned integers. Propositiona logic. Boolean algebra and canonical forms. Elementary combinatorial circuits: decoder, multiplexer. Arithmetic through Logic. ALU. Sequential machines: representations using FSM and "single-block" design. Flip-flops, registers. Design of dedicated machine according to the operating unit/control unit methodology.
2nd PART - Microprocessors: From dedicated machines to the universal machine. Technology, architecture, organization. Memory hierarchies. CPU-Memory-I/O transactions. Fetch and execution of machine instructions. Instruction types. Addressing modes. Design of a single machine instruction: coding and implementation (hardware of operating unit, control automaton). Bus, machine and wait cycles. CISC and RISC architectures. Performance. Assembly programming. Assembler, linker, loader.
Representation of signed/unsigned integers. Propositiona logic. Boolean algebra and canonical forms. Elementary combinatorial circuits: decoder, multiplexer. Arithmetic through Logic. ALU. Sequential machines: representations using FSM and "single-block" design. Flip-flops, registers. Design of dedicated machine according to the operating unit/control unit methodology.
2nd PART - Microprocessors: From dedicated machines to the universal machine. Technology, architecture, organization. Memory hierarchies. CPU-Memory-I/O transactions. Fetch and execution of machine instructions. Instruction types. Addressing modes. Design of a single machine instruction: coding and implementation (hardware of operating unit, control automaton). Bus, machine and wait cycles. CISC and RISC architectures. Performance. Assembly programming. Assembler, linker, loader.